1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices having a source region, a gate region, and a drain region, and in particular, to a method of manufacturing semiconductor devices in which impurities are implanted to the source and the drain region by using as a mask a gate pattern of a transistor (FET: Field Effect Transistor) having a metal-oxide semiconductor structure.
2. Description of the Prior Art
Semiconductor devices having a so-called MOS (Metal-Oxide Semiconductor) structure which employs a capacitor structure constituted by a metal-oxide semiconductor are widely known in the art. The semiconductor devices having the MOS structure are manufactured by a process in which various technical improvements such as self alignment, thin film formation, application of polycrystalline silicon, micro lithography, field isolation (LOCOS), ion implantation, etc., are included. By virtue of the technical improvement as mentioned above, an improvement in performance, a reduction of pattern, an improvement in integration density, and the like have been achieved one by one. Furthermore, such a method is introduced in which the density of elements is increased by overlapping polycrystalline silicon layers into double layers, or triple layers in a three-dimensional fashion.
As a technique of forming a minute pattern in these applied technologies, there is a self alignment technique which does not use a mask. This technique offers advantages in which highly accurate pattern alignment can be achieved without retaining a margin for mask alignment, degradation of performance and decrease in yield due to a deviation in positioning are small, and the number of times of use of mask can be reduced. Accordingly, the improvement in accuracy and the simplification of the manufacturing process can be achieved, and thus, the self alignment technique is widely used recently in a semiconductor manufacturing process.
In an electrode self alignment process for forming an electrode by the use of the self alignment technique mentioned above, for example, in the case of forming a silicon gate electrode, as shown in FIG. 5, an element isolating oxide film 103 is formed on an N type silicon substrate 101, and after forming a channel region 105 for controlling a threshold voltage, by an ion implantation of impurities, a gate oxide film 107 is formed. Then, after forming a gate material film 109 on the gate oxide film 107, a first resist pattern on the gate material film 109 is removed by etching. Following this, a second resist pattern 111 having openings defining a gate region and a drain region is formed. Subsequently, by using the gate material film 109 and the second resist pattern 111 as a mask, impurities such as p (phosphorus), B (boron), As (arsenic), or the like are implanted into the source region 113 and the drain region 115. This impurity implantation technique is primarily performed in order to enable to carry out introduction of low concentration impurities, doping through an insulator, or the like which is impossible or very difficult by a method of thermal diffusion.
Owing to the recent progress in the miniaturization technique, for example, in CMOS VLSIs (Complementary MOS Very Large Scale Integrated Circuit) having a channel length of 0.5 micrometers or less, the thickness of a gate electrode and a gate oxide film is made thin in accordance with a miniaturization pattern. Due to the formation of such thinner films of the gate electrode and the gate oxide film, a serious problem arises which has not posed any problem in the prior art technique.
Specifically, in the above-mentioned electrode self alignment technique, impurities are implanted through the gate material film as a mask. As a result, if the gate material film is formed with a sufficiently thick mask material with respect to a range of ions implanted therein, the ions will stop in the inside of the gate material film and will not reach into a substrate underlying the mask. However, due to the recent thinner film formation of the gate material film, the possibility of reaching of the ions into the inside of the substrate is increasing. Furthermore, even if the gate material film is designed to have a large thickness as compared with the range of ions taking into account the energy of implanted ions, the kind of ions, the state of a substrate, etc., for example, if a subsequent heat treatment is performed for the purpose of annealing for activating impurities, and for the purpose of oxidation of a semiconductor substrate, the impurities which have been stopped inside the gate material film will be thermally diffused into a channel region penetrating through a gate oxide film. Here, the diffusion of the impurities into the channel through the gate oxide film is referred to as "penetration of impurities through the oxide film" as is usually called. Since this penetration through the oxide film alters a preset impurity concentration in the channel, for example, a threshold voltage and a current characteristic of a MOS transistor will be varied from desired values. This, in turn causes non-uniformity in the quality of products, and causes reduction of the reproducibility, the rate of good products, the yield, etc., of the products. This effect of thermal diffusion of impurities is reported by semiconductor researchers. (For example, refer to the article by J. Y. C. Sun et al. "Study of Boron Penetration through Thin Oxide with P.sup.+ Polycilicon Gate", 1989 symposium on VLSI technology, p.17, 1989)
As a method of interrupting the thermal diffusion, it is known in the art to form a gate insulation film consisting of SiN or SiON.
However, since the SiN film contains many electron traps, the amount of electric charges trapped in the SiN film is not stabilized after a semiconductor device is completed. Accordingly, there is a problem in that the transistor characteristics including a threshold voltage, conductance, and the like are not stabilized, and that the transistor characteristics are changed due to trapping of electrons in the SiN film resulting in degradation of the reliability of the products.
Although the SiON film can relieve the problem posed by the SiN film, it is not sufficient to ensure the reliability of the products. Furthermore, the SiON film is inferior to the SiN film in the capability of interrupting the thermal diffusion of impurities.
Moreover, in order to form the gate insulation film consisting of SiON, it is necessary to perform a nitriding treatment under a high temperature in an atmosphere of NH.sub.3 or N.sub.2 after an SiO.sub.2 film is formed. Thus, a problem arises in that the number of processes is increased, and the productivity is lowered.